1. Field of the Invention
This invention relates generally to pipelined data converters, and more particularly to a system and a method for optimizing the power consumed by a pipelined analog-to-digital converter (ADC) with respect to the sampling frequency at which it is operating.
2. Description of the Prior Art
Any high performance pipelined ADC designed in accordance with a particular sampling frequency specification is optimized for that sampling frequency with respect to power consumption. Such an ADC therefore consumes unnecessary extra power while operating at sampling frequencies that are lower than the optimal highest sampling frequency. In view of the foregoing, there is a need in the pipelined data converter art for a technique to optimize the power consumed by the data converter with respect to the sampling rate.
To meet the above and other objectives, the present invention provides a system and method for optimizing the power consumed by a pipelined data converter with respect to the sampling rate at which it is operating.
In one aspect of the invention, a data converter bias current control circuit is provided to adjust the bias current associated with a pipelined ADC such that ADC power consumption is optimized over a range of sampling frequencies.
In another aspect of the invention, a self-adaptive biasing scheme is provided to optimize power consumption for a pipelined ADC with respect to sampling frequency.
According to embodiment of the present invention, a data converter bias circuit comprises a frequency-to-voltage converter (FVC) operational to convert a plurality of sampling frequencies to a plurality of output voltages, and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents, wherein the plurality of bias currents operate to bias operational amplifiers associated with the data converter such that data converter power consumption is reduced with decreasing sampling frequencies. One embodiment of the FVC comprises a lossy integrator configured to generate the plurality of output voltages such that the plurality of output voltages comprise of a varying component proportional to the input frequency on top of a DC component. One embodiment of the data converter bias circuit further comprises DC component removal circuitry configured to process the plurality of bias currents such that the DC components are substantially eliminated from the plurality of bias currents.